Leakage Minimization Technique For Nanoscale CMOS VLSI Based On Macro-Cell Modeling

This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fanout effect. The proposed approach uses a new precise macro-modeling of leakage current considering subthreshold leakage, gate tunneling leakage, body effect, stack effect, and fanout effect. The macro-model is developed for every gate in the library designed using 45nm BSIM4 model of Berkeley Predictive Technology Model (BPTM). The methodology applies to ISCAS85 benchmark circuits, and the experimental result shows that the proposed methodology using the proposed macro-model are within 4% difference comparing to Hspice. Index Terms Nanometer CMOS, Cell Characterization, Leakage Power, Subthreshold Leakage Current, Gate Tunneling Current. December 13, 2006 DRAFT IEEE DESIGN&TEST OF COMPUTERS 2